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1 features ? utilizes the avr ? risc architecture avr ? high-performance and low-power risc architecture ? 118 powerful instructions ? most single clock cycle execution ? 32 x 8 general-purpose working registers ? up to 10 mips throughput at 10 mhz data and nonvolatile program memory ? 2k bytes of in-system programmable flash endurance: 1,000 write/erase cycles ? 128 bytes internal ram ? 128 bytes of in-system programmable eeprom endurance: 100,000 write/erase cycles ? programming lock for flash program and eeprom data security peripheral features ? one 8-bit timer/counter with separate prescaler ? programmable watchdog timer with on-chip oscillator ? spi serial interface for in-system programming special microcontroller features ? low-power idle and power-down modes ? external and internal interrupt sources ? power-on reset circuit ? selectable on-chip rc oscillator specifications ? low-power, high-speed cmos process technology ? fully static operation power consumption at 4 mhz, 3v, 25 c ? active: 2.4 ma ? idle mode: 0.5 ma ? power-down mode: <1 a i/o and packages ? three programmable i/o lines (at90s/ls2323) ? five programmable i/o lines (at90s/ls2343) ? 8-pin pdip and soic operating voltages ? 4.0 - 6.0v (at90s2323/at90s2343) ? 2.7 - 6.0v (at90ls2323/at90ls2343) speed grades ? 0 - 10 mhz (at90s2323/at90s2343) ? 0 - 4 mhz (at90ls2323/at90ls2343) description the at90s/ls2323 and at90s/ls2343 are low-power, cmos, 8-bit microcontrollers based on the avr risc architecture. by executing powerful instructions in a single clock cycle, the at90s2323/2343 achieves throughputs approaching 1 mips per mhz allowing the system designer to optimize power consumption versus processing speed. rev. 1004cs?10/00 8-bit microcontroller with 2k bytes of in-system programmable flash at90s2323 at90ls2323 at90s2343 at90ls2343 pin configuration pdip/soic at90s/ls2343 at90s/ls2323 1 2 3 4 8 7 6 5 reset xtal1 xtal2 gnd vcc pb2 (sck/t0) pb1 (miso/int0) pb0 (mosi) 1 2 3 4 8 7 6 5 reset (clock) pb3 pb4 gnd vcc pb2 (sck/t0) pb1 (miso/int0) pb0 (mosi) (continued) note: this is a summary document. a complete document is available on our web site at www.atmel.com .
2 at90s2323/ls2323 and at90s2343/ls2343 the avr core combines a rich instruction set with 32 general-purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional cisc microcontrollers. block diagram figure 1. the at90s/ls2343 block diagram program counter internal oscillator watchdog timer stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counter instruction decoder data dir. reg. portb data register portb programming logic timing and control interrupt unit eeprom spi status register z y x alu portb drivers pb0 - pb4 reset vcc gnd control lines 8-bit data bus
3 at90s2323/ls2323 and at90s2343/ls2343 figure 2. the at90s/ls2323 block diagram the at90s2323/2343 provides the following features: 2k bytes of in-system programmable flash, 128 bytes eeprom, 128 bytes sram, 3 (at90s/ls2323)/5 (at90s/ls2343) general-purpose i/o lines, 32 general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable watchdog timer with internal oscillator, an spi serial port for flash memory downloading and two software-selectable power-saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, spi port and interrupt system to continue functioning. the power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset . the device is manufactured using atmel ? s high-density nonvolatile memory technology. the on-chip flash allows the pro- gram memory to be reprogrammed in-system through an spi serial interface. by combining an 8-bit risc cpu with isp flash on a monolithic chip, the atmel at90s2323/2343 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications. program counter internal oscillator watchdog timer stack pointer program flash mcu control register sram general purpose registers instruction register timer/ counter instruction decoder data dir. reg. portb data register portb programming logic timing and control oscillator interrupt unit eeprom spi status register z y x alu portb drivers pb0 - pb2 reset vcc gnd control lines 8-bit data bus
4 at90s2323/ls2323 and at90s2343/ls2343 the at90s2323/2343 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emulators and evaluation kits. comparison between at90s/ls2323 and at90s/ls2343 the at90s/ls2323 is intended for use with external quartz crystal or ceramic resonator as the clock source. the start-up time is fuse-selectable as either 1 ms (suitable for ceramic resonator) or 16 ms (suitable for crystal). the device has three i/o pins. the at90s/ls2343 is intended for use with either an external clock source or the internal rc oscillator as clock source. the device has five i/o pins. table 1 summarizes the differences in features of the two devices. pin descriptions at90s/ls2323 vcc supply voltage pin. gnd ground pin. port b (pb2..pb0) port b is a 3-bit bi-directional i/o port with internal pull-up resistors. the port b output buffers can sink 20 ma. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. port b also serves the functions of various special features. port pins can provide internal pull-up resistors (selected for each bit). the port b pins are tri-stated when a reset condition becomes active. reset reset input. an external reset is generated by a low level on the reset pin. reset pulses longer than 50 ns will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. xtal1 input to the inverting oscillator amplifier and input to the internal clock operating circuit. xtal2 output from the inverting oscillator amplifier. table 1. feature difference summary part at90s/ls2323 at90s/ls2343 on-chip oscillator amplifier yes no internal rc clock no yes pb3 available as i/o pin never internal clock mode pb4 available as i/o pin never always start-up time 1 ms/16 ms 16 s fixed
5 at90s2323/ls2323 and at90s2343/ls2343 pin descriptions at90s/ls2343 vcc supply voltage pin. gnd ground pin. port b (pb4..pb0) port b is a 5-bit bi-directional i/o port with internal pull-up resistors. the port b output buffers can sink 20 ma. as inputs, port b pins that are externally pulled low will source current if the pull-up resistors are activated. port b also serves the functions of various special features. port pins can provide internal pull-up resistors (selected for each bit). the port b pins are tri-stated when a reset condition becomes active. reset reset input. an external reset is generated by a low level on the reset pin. reset pulses longer than 50 ns will generate a reset, even if the clock is not running. shorter pulses are not guaranteed to generate a reset. clock clock signal input in external clock mode. clock options crystal oscillator the at90s/ls2323 contains an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in figure 3. xtal1 and xtal2 are input and output respectively. either a quartz crystal or a ceramic resonator may be used. it is recommended that the at90s/ls2343 be used if an external clock source is used, since this gives an extra i/o pin. figure 3. oscillator connection external clock the at90s/ls2343 can be clocked by an external clock signal, as shown in figure 4, or by the on-chip rc oscillator. this rc oscillator runs at a nominal frequency of 1 mhz (v cc = 5v). a fuse bit (rcen) in the flash memory selects the on-chip rc oscillator as the clock source when programmed ( ? 0 ? ). the at90s/ls2343 is shipped with this bit programmed. the at90s/ls2343 is recommended if an external clock source is used, because this gives an extra i/o pin. the at90s/ls2323 can be clocked by an external clock as well, as shown in figure 4. no fuse bit selects the clock source for at90s/ls2323.
6 at90s2323/ls2323 and at90s2343/ls2343 figure 4. external clock drive configuration architectural overview the fast-access register file concept contains 32 x 8-bit general-purpose working registers with a single clock cycle access time. this means that during one single clock cycle, one alu (arithmetic logic unit) operation is executed. two operands are output from the register file, the operation is executed and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing, enabling efficient address calculations. one of the three address pointers is also used as the address pointer for the constant table look-up function. these added function registers are the 16-bit x-register, y-register and z-register. figure 5. the at90s2323/2343 avr risc architecture gnd gnd external oscilator signal external oscilator signal nc xtal2 xtal1 pb3 at90s/ls2323 at90s/ls2343 1k x 16 program flash instruction register instruction decoder program counter control lines 32 x 8 general purpose registers alu status and test control registers interrupt unit spi unit 8-bit timer/counter watchdog timer i/o lines 128 x 8 eeprom data bus 8-bit avr at90s2323/2343 architecture 128 x 8 data sram direct addressing indirect addressing
7 at90s2323/ls2323 and at90s2343/ls2343 the alu supports arithmetic and logic functions between registers or between a constant and a register. single register operations are also executed in the alu. figure 5 shows the at90s2323/2343 avr risc microcontroller architecture. in addition to the register operation, the conventional memory addressing modes can be used on the register file as well. this is enabled by the fact that the register file is assigned the 32 lowermost data space addresses ($00 - $1f), allowing them to be accessed as though they were ordinary memory locations. the i/o memory space contains 64 addresses for cpu peripheral functions such as control registers, timer/counters, a/d converters and other i/o functions. the i/o memory can be accessed directly or as the data space locations following those of the register file, $20 - $5f. the avr has harvard architecture ? with separate memories and buses for program and data. the program memory is accessed with a two-stage pipeline. while one instruction is being executed, the next instruction is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system downloadable flash memory. with the relative jump and call instructions, the whole 1k address space is directly accessed. most avr instructions have a single 16-bit word format. every program memory address contains a 16- or 32-bit instruction. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effec- tively allocated in the general data sram and consequently, the stack size is only limited by the total sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the 8-bit stack pointer (sp) is read/write-accessible in the i/o space. the 128 bytes data sram + register file and i/o registers can be easily accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. figure 6. memory maps eeprom (128 x 8) $000 $07f eeprom data memory
8 at90s2323/ls2323 and at90s2343/ls2343 a flexible interrupt module has its control registers in the i/o space with an additional global interrupt enable bit in the st atus register. all the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the p ro- gram memory. the different interrupts have priority in accordance with their interrupt vector position. the lower the interrupt vector address, the higher the priority.
9 at90s2323/ls2323 and at90s2343/ls2343 notes: 1. for compatibility with future devices, reserved bits should be written to zero if accessed. reserved i/o memory address es should never be written. 2. some of the status flags are cleared by writing a logical ? 1 ? to them. note that the cbi and sbi instructions will operate on all bits in the i/o register, writing a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions wo rk with registers $00 to $1f only. at90s2323/2343 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page $3f ($5f) sreg i t h s v n z c page 17 $3e ($5e) reserved $3d ($5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 page 17 $3c ($5c) reserved $3b ($5b) gimsk -int0 - - - - - - page 22 $3a ($5a) gifr -intf0 page 23 $39 ($59) timsk - - - - - -toie0 - page 23 $38 ($58) tifr - - - - - -tov0 - page 23 $37 ($57) reserved $36 ($56) reserved $35 ($55) mcucr - -sesm - - isc01 isc00 page 24 $34 ($54) mcusr - - - - - - extrf porf page 21 $33 ($53) tccr0 - - - - - cs02 cs01 cs00 page 27 $32 ($52) tcnt0 timer/counter0 (8 bits) page 28 $31 ($51) reserved $30 ($50) reserved $2f ($4f) reserved $2e ($4e) reserved $2d ($4d) reserved $2c ($4c) reserved $2b ($4b) reserved $2a ($4a) reserved $29 ($49) reserved $28 ($48) reserved $27 ($47) reserved $26 ($46) reserved $25 ($45) reserved $24 ($44) reserved $23 ($43) reserved $22 ($42) reserved $21 ($41) wdtcr - - - wdto wde wdp2 wdp1 wdp0 page 29 $20 ($40) reserved $1f ($3f) reserved $1e ($3e) eear - eeprom address register page 30 $1d ($3d) eedr eeprom data register page 30 $1c ($3c) eecr - - - - - eemw eewe eere page 30 $1b ($3b) reserved $1a ($3a) reserved $19 ($39) reserved $18 ($38) portb - - - portb portb portb portb portb page 32 $17 ($37) ddrb - - - ddb4 ddb3 ddb2 ddb1 ddb0 page 32 $16 ($36) pinb - - - pinb4 pinb3 pinb2 pinb1 pinb0 page 33 $15 ($35) reserved ? reserved $00 ($20) reserved
10 at90s2323/ls2323 and at90s2343/ls2343 instruction set summary mnemonic operands description operation flags # clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl, k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd ? rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd ? k z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl ? k z,c,n,v,s 2 sbc rd, rr subtract with carry two registers rd rd ? rr ? c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd ? k ? c z,c,n,v,h 1 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? kz,n,v1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusive or registers rd rd rr z,n,v 1 com rd one ? s complement rd $ff ? rd z,c,n,v 1 neg rd two ? s complement rd $00 ? rd z,c,n,v,h 1 sbr rd, k set bit(s) in register rd rd v k z,n,v 1 cbr rd, k clear bit(s) in register rd rd ? ($ff ? k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd $ff none 1 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc z none 3 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd, rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd, rr compare rd ? rr z,n,v,c,h 1 cpc rd, rr compare with carry rd ? rr ? c z,n,v,c,h 1 cpi rd, k compare register with immediate rd ? k z,n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in register is set if (rr(b) = 1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b) = 0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (r(b) = 1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc = pc + k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc = pc + k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v = 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v = 1) then pc pc + k + 1 none 1/2 brhs k branch if half-carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half-carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t-flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t-flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1/2
11 at90s2323/ls2323 and at90s2343/ls2343 data transfer instructions mov rd, rr move between registers rd rr none 1 ldi rd, k load immediate rd k none 1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, -x load indirect and pre-dec. x x ? 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, -y load indirect and pre-dec. y y ? 1, rd (y) none 2 ldd rd, y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z + 1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st -x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st -y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q, rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q, rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 in rd, p in port rd p none 1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 bit and bit-test instructions sbi p, b set bit in i/o register i/o(p,b) 1 none 2 cbi p, b clear bit in i/o register i/o(p,b) 0 none 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) = c, rd(n+1) rd(n), c = rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) = c, rd(n) rd(n+1), c = rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n = 0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) = rd(7..4), rd(7..4) = rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1c1 clc clear carry c 0c1 sen set negative flag n 1n1 cln clear negative flag n 0n1 sez set zero flag z 1z1 clz clear zero flag z 0z1 sei global interrupt enable i 1i1 cli global interrupt disable i 0i1 ses set signed test flag s 1s1 cls clear signed test flag s 0s1 sev set two ? s complement overflow v 1v1 clv clear two ? s complement overflow v 0v1 set set t in sreg t 1t1 clt clear t in sreg t 0t1 seh set half-carry flag in sreg h 1h1 clh clear half-carry flag in sreg h 0h1 nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 3 wdr watchdog reset (see specific descr. for wdr/timer) none 1 instruction set summary (continued) mnemonic operands description operation flags # clocks
12 at90s2323/ls2323 and at90s2343/ls2343 note: the speed grade refers to maximum clock rate when using an external crystal or external clock drive. the internal rc oscil lator has the same nominal clock frequency for all speed grades. ordering information power supply speed (mhz) ordering code package operation range 2.7 - 6.0v 4 at90ls2323-4pc at90ls2323-4sc 8p3 8s2 commercial (0 c to 70 c) at90ls2323-4pi at90ls2323-4si 8p3 8s2 industrial (-40 c to 85 c) 4.0 - 6.0v 10 at90s2323-10pc at90s2323-10sc 8p3 8s2 commercial (0 c to 70 c) at90s2323-10pi at90s2323-10si 8p3 8s2 industrial (-40 c to 85 c) 2.7 - 6.0v 4 at90ls2343-4pc at90ls2343-4sc 8p3 8s2 commercial (0 c to 70 c) at90ls2343-4pi at90ls2343-4si 8p3 8s2 industrial (-40 c to 85 c) 4.0 - 6.0v 10 at90s2343-10pc at90s2343-10sc 8p3 8s2 commercial (0 c to 70 c) at90s2343-10pi at90s2343-10si 8p3 8s2 industrial (-40 c to 85 c) package type 8p3 8-lead, 0.300" wide, plastic dual inline package (pdip) 8s2 8-lead, 0.200" wide, plastic gull wing small outline package (eiaj soic)
at90s2323/ls2323 and at90s2343/ls2343 13 packaging information .400 (10.16) .355 (9.02) pin 1 .280 (7.11) .240 (6.10) .037 (.940) .027 (.690) .300 (7.62) ref .210 (5.33) max seating plane .100 (2.54) bsc .015 (.380) min .022 (.559) .014 (.356) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .325 (8.26) .300 (7.62) 0 15 ref .430 (10.9) max .012 (.305) .008 (.203) .020 (.508) .012 (.305) .213 (5.41) .205 (5.21) .330 (8.38) .300 (7.62) pin 1 .050 (1.27) bsc .212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78) .013 (.330) .004 (.102) 0 8 ref .010 (.254) .007 (.178) .035 (.889) .020 (.508) 8p3, 8-lead, 0.300" wide, plastic dual inline package (pdip) dimensions in inches and (millimeters) jedec standard ms-001 ba 8s2, 8-lead, 0.200" wide, plastic gull wing small outline (eiaj soic) dimensions in inches and (millimeters)
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